1. Field of the Invention
The present invention relates to an apparatus for testing a synchronous dynamic random access memory (DRAM) which is a semiconductor memory, and more particularly to a multi-bank testing apparatus for a synchronous DRAM, which allows all banks of the synchronous DRAM to simultaneously carry out their write and read operations in a test mode, thereby being capable of testing the entire bank in order to reduce the test time being likely to increase in accordance with an increased memory integration degree.
2. Description of the Related Art
Generally, a synchronous DRAM includes a plurality of row address strobe (RAS) generating circuits corresponding respectively to banks of the synchronous DRAM. Each of the RAS-generating circuits is enabled in response to a bank selection address signal adapted to select a bank associated with the RAS-generating circuit, thereby establishing row paths for the selected bank. The synchronous DRAM also includes a plurality of column address strobe (CAS) generating circuits corresponding respectively to the banks of the synchronous DRAM. Each of the CAS-generating circuits is enabled in response to a bank selection address signal adapted to select a bank associated with the CAS-generating circuit, thereby establishing column paths for the selected bank.
The above operations of the row and column address strobe generating circuits will now be described in conjunction with FIGS. 1 and 2.
When a row active command is inputted to a synchronous DRAM in a normal operation mode, it enables a row address strobe signal which is a command signal for enabling RAS-generating circuits. This row address strobe signal is applied to RAS-generating circuits (denoted by "rasgen" in FIG. 1) 3 of all banks in the synchronous DRAM. Simultaneously, a bank selection address signal, which selects one of the banks, is applied to RAS-generating circuits 3 of all banks. Only the RAS-generating circuit 3 of the bank selected by the received bank selection address signal is enabled, based on the received row address strobe signal, to output a row address strobe enable signal, thereby establishing row paths for the selected bank. As a result, a word line associated with the enabled bank is enabled.
On the other hand, when a column active command is inputted to the synchronous DRAM, it enables a column address strobe signal which is a command signal for enabling CAS-generating circuits. This column address strobe signal is applied to CAS-generating circuits (denoted by "casgen" in FIG. 1) 4 of all banks in the synchronous DRAM. Simultaneously, a bank selection address signal, which selects one of the banks, is applied to CAS-generating circuits 4 of all banks. Only the CAS-generating circuit 4 of the bank selected by the received bank selection address signal is enabled, based on the received column address strobe signal, to output a column address strobe enable signal, thereby establishing column paths for the selected bank. As a result, a signal Yi, serving to couple each of bit lines to an associated one of local data bus lines LDB in an enable state thereof, is enabled. Accordingly, it is possible to carry out data read and write operations for the selected bank.
The above-mentioned data paths will be described in more detail, in conjunction with FIG. 1.
First, a description will be made in regard to the write paths.
Buffered data from each of data input buffers 11 is sent to an associated one of global write data bus lines GWDB, and is then sent to an associated one of local data bus lines LDB in accordance with an operation of an associated one of write drivers WD.
In this state, when the signal Yi, serving to couple each local data bus line LDB to an associated one of bit lines in an enable state thereof, is enabled, the data from each local data bus line LDB is applied to an associated one of cells 1 via an associated bit line, so that it is stored in the associated cell 1.
Next, a description will be made in regard to the read paths.
When data from each cell 1 in a selected bank is sent to an associated bit line in accordance with a row active command, the signal Yi is enabled in response to the row active command, thereby causing the data from the bit line to be transmitted to an associated local data bus line LDB. The data from the local data bus line LDB is then sent to an associated input/output sense amplifier 5 which, in turn, amplifies the data. The amplified data is subsequently transmitted to an associated global read data bus line GRDB, so that it is output through an associated data output buffer 12.
As mentioned above, a synchronous DRAM, which consists of Nbanks, conducts row and column activating operations for only one particular bank selected by a bank selection address BA every time the bank selection address BA is generated. For this reason, the testing operation for such a synchronous DRAM is carried out for one bank.
In order to test the entire bank of the synchronous DRAM, it is necessary to conduct the testing operation by N times corresponding to the number of banks in the synchronous DRAM. This results in a lengthened test time.